Machine Specification

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Instruction Fields

Condition codes

cccc	Name			Condition	Description
0000	-nc	-pl	-nmi	0==NF	Negative flag Clear	PLus	Not MInus
0001	-zc		-neq	0==ZF	Zero flag Clear		Not EQual
0010	-vc		-nov	0==VF	oVerflow flag Clear		No OVerflow
0011	-cc	-hs	-nlo	0==CF	Carry flag Clear	Higher or Same	not lower
0100		-hi	-nls	0==~CF\|ZF		HIgher	not lower or same
0101		-ge	-nlt	0==NF^VF		Greater or Equal	not lesser than
0110		-gt	-nle	0==(NF^VF)\|ZF		Greater Than	not lesser or equal
0111	-sr			N/A	to SubRoutine
1000	-ns	-mi	-npl	1==NF	Negative flag Set	MInus	not plus
1001	-zs	-eq		1==ZF	Zero flag Set	EQual
1010	-vs	-ov		1==VF	oVerflow flag Set	OVerflow
1011	-cs	-lo	-nhs	1==CF	Carry flag Set	LOwer	not higher or same
1100		-ls	-nhi	1==~CF\|ZF		Lower or Same	not higher
1101		-lt	-nge	1==NF^VF		Lesser Than	not greater or equal
1110		-le	-ngt	1==(NF^VF)\|ZF		Lesser or Equal	not greater than
1111	jmp/bra			1==1	always

Effective Addresses

mmmxxx	Syntax	Pseudocode	Description
000xxx	Dx	D[x]	Data
001xxx	Ax	A[x]	Address
010xxx	@x+	(s)M[A[x]++]	post-increment deferred
011xxx	@x-	(s)M[--A[x]]	pre-decrement deferred
100xxx	@x	(s)M[A[x]]	deferred
101xxx	@x.H#dsp16	(s)M[A[x]+(H)M[IP++]]	base plus Halfword deferred
110xxx	@x.W#dsp32	(s)M[A[x]+(W)M[IP++]]	base plus Word deferred
111000	$	SR	status register
111010	#imm	(s)M[IP++]	immediate memory
111101	?H#dsp16	(s)M[IP+(H)M[IP++]]	relative Halfword deferred
111110	?W#dsp32	(s)M[IP+(W)M[IP++]]	relative Word deferred

Memory Access Scales

ss	as	ms	rm	Name	Mode
00	B	1	Dy	Byte	Data
01	H	2	Dy	Halfword	Data
10	W	4	Dy	Word	Data
11	A	4	Ay	Address	Address

Instructions

0123456789ABCDEF	Name	x	Rw	R-	BHW	Description
0000000000000000	NOP				...	No OPeration
0000000000010000	RFI				...	Return From Interupt
0000000000011000	UNLNK				...	UNLiNK
00000000ss110000	RFS	s		CI	.HW	Return From Subroutine
00000000ss111000	LNK	s		CI	.HW	LiNK
00000001ssmmmxxx	CMPI	s	mx	CI	BHW	CoMPare (Immediate)
00000010ssmmmxxx	ADDI	s	mx	CI	BHW	ADD (Immediate)
00000011ssmmmxxx	SUBI	s	mx	CI	BHW	SUBtract (Immediate)
00000100ssmmmxxx	XORI	s	mx	CI	BHW	eXclusive OR (Immediate)
00000101ssmmmxxx	ORI	s	mx	CI	BHW	OR (Immediate)
00000110ssmmmxxx	ANDI	s	mx	CI	BHW	AND (Immediate)
00000111ssmmmxxx	STI	s	mx	CI	BHW	STore (Immediate)
00001000ssmmmxxx	NOT	s	mx		BHW	NOT
00001001ssmmmxxx	NEG	s	mx		BHW	NEGate
00001010ssmmmxxx	ADC	s	mx		BHW	AdD w/ Carry
00001011ssmmmxxx	SBC	s	mx		BHW	SuBtract w/ Carry
00001100ssmmmxxx	CLR	s	mx		BHW	CLeaR
00001101ssmmmxxx	REV	s	mx		BHW	REVerse
00001110ssmmmxxx	EXT	s	mx		BHW	EXTend sign
00001111ssmmmxxx	TST	s	mx		BHW	TeST against zero
00010yyy00000xxx	HMULU		Dy	Dx	...	High-word MULtiply (Unsigned)
00010yyy00010xxx	HMULS		Dy	Dx	...	High-word MULtiply (Signed)
00010yyy00011xxx	MUL		Dy	Dx	...	MULtiply
00010yyy00100xxx	DIVU		Dy	Dx	...	DIVide (Unsigned)
00010yyy00101xxx	DIVS		Dy	Dx	...	DIVide (Signed)
00010yyy00110xxx	MODU		Dy	Dx	...	MODulo (Unsigned)
00010yyy00111xxx	MODS		Dy	Dx	...	MODulo (Signed)
00011yyy00mmmxxx	LSL		Dy	mx	B..	Logical Shift Left
00011yyy01mmmxxx	LSR		Dy	mx	B..	Logical Shift Right
00011yyy10mmmxxx	ASR		Dy	mx	B..	Arithmetic Shift Right
00011yyy11mmmxxx	ROR		Dy	mx	B..	ROtate Right
01000yyyqqqqqqqq	LDQ		Dy	Cq	...	LoaD (Quick)
01001yyyqqqqqqqq	CMPQ		Dy	Cq	...	CoMPare (Quick)
01010qqqssmmmxxx	ADDQ	s	mx	Cq	BHW	ADD (Quick)
01011qqqssmmmxxx	SUBQ	s	mx	Cq	BHW	SUBtract (Quick)
01100qqqqqmmmxxx	LSLQ		mx	Cq	..W	Logical Shift Left (Quick)
01101qqqqqmmmxxx	LSRQ		mx	Cq	..W	Logical Shift Right (Quick)
01110qqqqqmmmxxx	ASRQ		mx	Cq	..W	Arithmetic Shift Left (Quick)
01111qqqqqmmmxxx	RORQ		mx	Cq	..W	ROtate Right (Quick)
0111100000mmmxxx	RRC		mx		..W	Rotate Right through Carry
10000yyyssmmmxxx	LD	s	Ry	mx	BHW	LoaD
10001yyyssmmmxxx	CMP	s	Ry	mx	BHW	CoMPare
10010yyyssmmmxxx	ADD	s	Ry	mx	BHW	ADD
10011yyyssmmmxxx	SUB	s	Ry	mx	BHW	SUBtract
10100yyyssmmmxxx	XOR	s	Ry	mx	BHW	eXclusive OR
10101yyyssmmmxxx	OR	s	Ry	mx	BHW	OR
10110yyyssmmmxxx	AND	s	Ry	mx	BHW	AND
10111yyyssmmmxxx	ST	s	mx	Ry	BHW	STore
1110ccccqqqqqqqq	Bcc		Cq		...	Branch
1111ccccssmmmxxx	Jcc	s	mx		BHW	Jump